Signal Integrity Training with HyperLynx®

ONLINE Signal Integrity & EMC Course - "RIGHT THE FIRST TIME"   with HyperLynx  

SIGNAL INTEGRITY & EMC with Hyperlynx course on demand at your desk without leaving your workspace 

No-campus attendance No commuting No travel cost No deadline pressure. 

Enroll any time and enjoy affordable fee.

 

RIGHT THE FIRST TIME” with HyperLynx® is a Signal Integrity and Electromagnetic Compliance “how to do it right” class that gives students a well-rounded explanation of proper high-speed system design.  The course is based on a design methodology developed by a major telecommunications company, which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time.    “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests… on the first try! 

Target Audience: Engineers and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems that will work reliably at full speed and still remain quiet enough to pass regulatory EMI tests.  The basic methodology upon which this class is based was documented to achieve repeatable first pass success as a standard practice.

Why Should I attend this Training?
Increasingly fast edge rates in today’s integrated circuits (ICs) cause detrimental high-speed effects, even in PCB designs running at low operating frequencies. As driver ICs switch faster, a growing volume of boards suffers from signal degradation, including over/undershoot, ringing, glitching, crosstalk, and timing problems. When degradation becomes serious enough, the logic on a board can fail.

Any Electrical Engineer, CAD Layout Designer, or Technical Manager tired of design which works now and which do not works after some time, 2 out of 10 board works can get a nightmare whether the next lot of production run is going to work or whether its going to pass FCC & CISPR compliance test would find this class extremely useful. Students who have implemented this methodology have regularly produced complex designs that do indeed work correctly on the first implementation.  On average, that saves about $10000 and two months on the average system using 2006 technology.   Any financially responsible manager will agree that saving two designs turns on the typical system results in huge savings and potentially even larger profits by getting to market earlier.

“RIGHT THE FIRST TIME” with HyperLynx® is delivered in 2 Parts, Part I and Part II                                         

PART-I Content

Basic Signal Integrity including board layer stack-up specification, high-speed routing topology, space, trace, termination practices, and return current control. Get this wrong and the system will reward you with a host of problems including False Clock, False Data, Negative Timing Margins, Clock Jitter, Excessive EMI as well as a host of Manufacturing and Reliability issues.

Power Delivery is a lot more than one 0.1uF and five 0.01uF caps per pin.  Power delivery depends upon stack-up, capacitor selection, placement, mounting technique, and quantity.  Typical target impedance for memory systems must be around 0.1 ohm from DC to the highest frequency of interest.  The highest frequency of interest is most likely in the microwave region.  Poor design can result in power delivery impedance poles and inter plane resonance.  Many of the mysterious SI and EMI issues can be traced directly to poor power delivery design.

Root causes and cures for EMI.  The class’s primary approach is to stop the noise at the source.  If noise is eliminated at the source, you do not need to chase it around the board.  The recent proliferation of ASIC’s from hell has prompted us to add a section on shielding and filtering.  If the problem is in the device, not the board, and you can not find a better behaved substitute for that device, your only choice is to shield and filter. 

Single Ended Bus Issues.   If you have a memory or address bus with both high and low speed devices, do the high speed devices belong close to the processor with the low speed devices farther away, or vice versa?  How do you terminate?  What about option slots?

How LVDS really works.  With the huge noise margin available using LVDS devices, you can use almost any interconnect scheme.  However there can be other complications like Cross Talk and EMI if you do it incorrectly.
 
Giga Bit Serial / SERDES interface routing issues …PCI Express We explain what is important and also debunk some of the popular myths about routing these types of interfaces.

The Analog / Digital Interface i.e. Isolation vs. Communication

Understanding the issues related to “quiet grounds.”

Connectors, Board-to-Board SI, EMI, and Power Issues

Chip Level Package Issues and how to defend against them.

Basic Shielding Theory as it applies to Switching Power Supplies

Critical elements in an effective high-speed system design process.  Simply performing a solid pre-layout design review and including the correct personnel can raise you first time odds of success at least 50%.  Implementing a full process can result in first time success 99% of the time.

PART-II Content

NOTE: All lessons are documented with relevant Screen-shots and Audio-Video demonstrations which becomes much easier to kick start Hyperlynx & jump on a particular feature to make your learning interesting & easy
 
How LineSim Works 
Simulating a Simple Clock Net In LineSim 
Fixing the Clock Net 6 
A Series-Terminated Net with IBIS Model 
EMC Analysis of the Clock Net & Terminated Clock Net 
About LineSim’s Free-Form Schematic Editor 
Signal-Integrity of a DDR Data Path 
About Modeling ICs 
How LineSim's Crosstalk Analysis Works 
Differential-Signal Analysis 
Crosstalk Exp: Planning Minimum Trace Separation on a Bus 
Differential-Trace Example 
Achieving a Specific Differential Impedance 
LineSim's GHz Features 
Lossy Simulations 
Viewing Loss in the Frequency Domain 
Integrated SPICE Simulations 
Touchstone (S-Parameter) Modeling 
Eye Diagrams and Multi-Bit Stimulus USB 2.0 Example 
Modeling a PCB Stackup 
Introduction 
Overview of the Stackup Editor 
How to Do Impedance Planning 
Impedance Planning for Differential Pairs 
HyperLynx Demonstration Post-Layout (BoardSim) 
Post-Layout Analysis: BoardSim and Batch Mode 
Introduction 
How BoardSim Works 
Translating your Board into BoardSim's Format 
Batch Analysis of the Entire Board for Signal-Integrity, Crosstalk, and 
EMC Problems 
Detailed Batch Analysis of Critical Nets 
BoardSim's Crosstalk and Differential-Signal Features 
How BoardSim's Crosstalk Analysis Works 
Using BoardSim Crosstalk for Differential-Signal Analysis 
Quick Analysis: Generating a Crosstalk Strength Report for an Entire PCB 
Running Detailed Batch-Mode Crosstalk Simulations 
BoardSim's GHz Features 
Advanced Via Modeling 
Visualizing a Via’s Geometric/Electrical Characteristics 
BoardSim's MultiBoard Feature 
Quick-Start 
Using Hyperlynx for Post PCB layout Simulation 
HyperLynx - New Features and Enhancements 
Background Information on Signal-Integrity, Crosstalk, EMC, 
Hyperlynx and GHz Analysis 
PCB Design Analysis Software Guidelines 
HyperLynx Applications 
Input Guidelines for HyperLynx BoardSim 
HyperLynx Input/Output File Types 
Modeling ICs / Why IC Models are Important 
IC Modeling with HyperLynx 
Conclusion 
 
Disclaimer: Due to CEDA’s policy of continuous improvement, specific course change without notice. Therefore, this agenda should be taken as a guide only part of any agreement between CEDA and any other party

 

Teaching Method ... Explain, Demonstrate, Do        

The instructor will explain the problem and an appropriate method to solve that problem. – Audio & Slides Presentation
The instructor will demonstrate the solution using industry standard software tools. – Audio Video Demonstration
The students will do the work for themselves using lab computers and sample problems.

The students perform computer-based labs to help lock in understanding of the physics behind classical high-speed design problems.  This also gives them the freedom to try their own examples.  Simply hearing information results in about a 30% retention rate.  Seeing a demonstration will raise the retention rate closer 50%.  If you actually do the work on something meaningful to the student, the retention is over 80%.

The purpose of this class is not to get into complex formulae and higher math.  There are perfectly good simulators to do the heavy lifting.  The purpose is to give layout designers and EE’s the tools to make their next design a quiet, reliable, full speed system on the first try.

You will learn how to

  • Create and simulate LineSim cell-based and free-form schematics
  • Investigate termination strategies
  • Investigate stack-up strategies
  • Translate design databases
  • Identify and debug SI and Crosstalk issues
  • Read eye diagrams and how to specify a mask
  • Simulate EMC and evaluate the results
  • Assign models and component values
  • Evaluate SI and Crosstalk issues
  • Translate PCB layout databases
  • Run BoardSim simulations interactively and in batch mode
  • Run BoardSim for both single and multi-board projects
  • Evaluate batch mode simulation reports to identify potential problems

Prerequisites

Familiarity with High-speed PCB concepts

The course kit comes with:

  1. Simulation Software evaluation CD
  2. Printed Training Manual 
  3. MULTIMEDIA PEN-DRIVE with audio- video Classroom tutorial just likes Live session                                                         
  4. Hyperlynx reference design and LAB session files                          
  5. Certificate of participation
  6. Right the First Time – Practical Handbook on Signal integrity by LEE.W.RITCHEY – 639 pages in PDF Format                                  
  7. Support– one month

Support


 India Phone No.: +91-9810338939
 

 

 


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